Maxim Integrated MAX32665 - Page 16

MAX32665-MAX32668 User Guide
Maxim Integrated Page 16 of 457
Table 4-36: Buck Regulator Output Ready Register ................................................................................................................... 77
Table 4-37: Zero Cross Calibration VREGO_A Register .............................................................................................................. 77
Table 4-38: Zero Cross Calibration VREGO_B Register .............................................................................................................. 78
Table 4-39: Zero Cross Calibration VREGO_C Register .............................................................................................................. 78
Table 4-40: Zero Cross Calibration VREGO_D Register .............................................................................................................. 78
Table 4-41: Power Sequencer and Always-On Domain Register Summary ............................................................................... 78
Table 4-42: Low Power Control Register ................................................................................................................................... 79
Table 4-43: GPIO0 Low Power Wakeup Status Flags ................................................................................................................. 80
Table 4-44: GPIO0 Low Power Wakeup Enable Registers .......................................................................................................... 80
Table 4-45: GPIO1 Low Power Wakeup Status Flags ................................................................................................................. 80
Table 4-46: GPIO1 Low Power Wakeup Enable Registers .......................................................................................................... 80
Table 4-47: Peripheral Low Power Wakeup Status Flags ........................................................................................................... 81
Table 4-48: Peripheral Low Power Wakeup Enable Register ..................................................................................................... 82
Table 4-49: RAM Shutdown Control Register ............................................................................................................................ 83
Table 4-50: Low Power VDD Power Down Register ................................................................................................................... 84
Table 4-51: BACKUP Return Vector Register ............................................................................................................................. 85
Table 4-52: BACKUP AoD Register ............................................................................................................................................. 85
Table 4-53: Global Control Register Summary ........................................................................................................................... 85
Table 4-54: System Control Register .......................................................................................................................................... 86
Table 4-55: Reset Register 0 ...................................................................................................................................................... 87
Table 4-56: System Clock Control Register ................................................................................................................................ 90
Table 4-57: Power Management Register ................................................................................................................................. 92
Table 4-58: Peripheral Clock Divisor Register ............................................................................................................................ 93
Table 4-59: Peripheral Clock Disable Register 0 ........................................................................................................................ 94
Table 4-60: Memory Clock Control Register .............................................................................................................................. 96
Table 4-61: Memory Zeroization Control Register .................................................................................................................... 98
Table 4-62: System Status Flag Register .................................................................................................................................. 100
Table 4-63: Reset Register 1 .................................................................................................................................................... 100
Table 4-64: Peripheral Clock Disable Register 1 ...................................................................................................................... 102
Table 4-65: Event Enable Register ........................................................................................................................................... 105
Table 4-66: Revision Register ................................................................................................................................................... 106
Table 4-67: System Status Interrupt Enable Register .............................................................................................................. 106
Table 4-68: Error Correction Coding Error Register ................................................................................................................. 106
Table 4-69: Error Correction Not Double Error Detected Register .......................................................................................... 107
Table 4-70: Error Correction Coding Interrupt Enable Register ............................................................................................... 109
Table 4-71: Error Correction Coding Address Register ............................................................................................................ 110
Table 4-72: Bluetooth LDO Control Register............................................................................................................................ 110
Table 4-73: Bluetooth LDO Delay Count Register .................................................................................................................... 112
Table 4-74: General Purpose 0 Register .................................................................................................................................. 112
Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register ................................................................................... 112
Table 4-76: Function Control Register Summary ..................................................................................................................... 113
Table 4-77: Function Control Register 0 .................................................................................................................................. 113
Table 4-78: AES Key Register Summary ................................................................................................................................... 114
Table 4-79: AES Key 0 and 1 Registers ..................................................................................................................................... 114
Table 4-80: AES Key 2 and 3 Registers ..................................................................................................................................... 114
Table 5-1: MAX32665—MAX32668 Interrupt Vector Table .................................................................................................... 115
Table 6-1: MAX32665—MAX32668 GPIO Pin Count ............................................................................................................... 119
Table 6-2: MAX32665—MAX32668 GPIO and Alternate Function Matrix, 140 WLP .............................................................. 120
Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration ................................................................................................... 121
Table 6-4: MAX32665—MAX32668 Input Mode Configuration .............................................................................................. 121
Table 6-5: MAX32665—MAX32668 Output Mode Configuration ........................................................................................... 122
Table 6-6: MAX32665—MAX32668 GPIO Port Interrupt Vector Mapping .............................................................................. 122
Table 6-7: MAX32665―MAX32668 GPIO Wakeup Interrupt Vector ...................................................................................... 124