MAX32665-MAX32668 User Guide
Maxim Integrated Page 17 of 457
Table 6-8: GPIO Register Summary .......................................................................................................................................... 125
Table 6-9: GPIO Port n Configuration Enable Bit 0 Register .................................................................................................... 126
Table 6-10: GPIO Port n Configuration Enable Atomic Set Bit 0 Register ................................................................................ 126
Table 6-11: GPIO Port n Configuration Enable Atomic Set Bit 0 Register ................................................................................ 126
Table 6-12: GPIO Port n Output Enable Register ..................................................................................................................... 126
Table 6-13: GPIO Port n Output Enable Atomic Set Register ................................................................................................... 127
Table 6-14: GPIO Port n Output Enable Atomic Clear Register ............................................................................................... 127
Table 6-15: GPIO Port n Output Register ................................................................................................................................. 127
Table 6-16: GPIO Port n Output Atomic Set Register .............................................................................................................. 127
Table 6-17: GPIO Port n Output Atomic Clear Register ........................................................................................................... 127
Table 6-18: GPIO Port n Input Register .................................................................................................................................... 128
Table 6-19: GPIO Port n Interrupt Mode Register ................................................................................................................... 128
Table 6-20: GPIO Port n Interrupt Polarity Register ................................................................................................................ 128
Table 6-21: GPIO Port n Input Enable Register ........................................................................................................................ 128
Table 6-22: GPIO Port n Interrupt Enable Register .................................................................................................................. 129
Table 6-23: GPIO Port n Interrupt Enable Atomic Set Register................................................................................................ 129
Table 6-24: GPIO Port n Interrupt Enable Atomic Clear Register ............................................................................................ 129
Table 6-25: GPIO Port n Interrupt Status Register ................................................................................................................... 129
Table 6-26: GPIO Port n Interrupt Clear Register..................................................................................................................... 129
Table 6-27: GPIO Port n Wakeup Enable Register ................................................................................................................... 130
Table 6-28: GPIO Port n Wakeup Enable Atomic Set Register ................................................................................................. 130
Table 6-29: GPIO Port n Wakeup Enable Clear Register .......................................................................................................... 130
Table 6-30: GPIO Port n Interrupt Dual Edge Mode Register .................................................................................................. 130
Table 6-31: GPIO Port n Pullup Pulldown Selection 0 Register ................................................................................................ 130
Table 6-32: GPIO Port n Pullup Pulldown Selection 1 Register ................................................................................................ 131
Table 6-33: GPIO Port n Configuration Enable Bit 1 Register .................................................................................................. 131
Table 6-34: GPIO Port n Configuration Enable Atomic Set, Bit 1 Register ............................................................................... 131
Table 6-35: GPIO Port n Configuration Enable Atomic Clear, Bit 1 Register ............................................................................ 131
Table 6-36: GPIO Port n Configuration Enable Bit 2 Register .................................................................................................. 132
Table 6-37: GPIO Port n Configuration Enable Atomic Set Bit 2 Register ................................................................................ 132
Table 6-38: GPIO Port n Configuration Enable Atomic Clear Bit 2 Register ............................................................................. 132
Table 6-39: GPIO Port n Output Drive Strength Bit 0 Register ................................................................................................ 132
Table 6-40: GPIO Port n Output Drive Strength Bit 0 Register ................................................................................................ 132
Table 6-41: GPIOn Pulldown/Pullup Strength Select Register ................................................................................................. 133
Table 6-42: GPIOn Supply Voltage Select Register .................................................................................................................. 133
Table 7-1: MAX32665—MAX32668 Internal Flash Memory Organization .............................................................................. 134
Table 7-2: Valid Addresses Flash Writes .................................................................................................................................. 135
Table 7-3: Flash Controller Registers ....................................................................................................................................... 137
Table 7-4: Flash Controller Address Pointer Register .............................................................................................................. 138
Table 7-5: Flash Controller Clock Divisor Register ................................................................................................................... 138
Table 7-6: Flash Controller Control Register ............................................................................................................................ 138
Table 7-7: Flash Controller Interrupt Register ......................................................................................................................... 139
Table 7-8: Flash Controller ECC Data Register ......................................................................................................................... 140
Table 7-9: Flash Controller Data Register 0 ............................................................................................................................. 140
Table 7-10: Flash Controller Data Register 1 ........................................................................................................................... 140
Table 7-11: Flash Controller Data Register 2 ........................................................................................................................... 140
Table 7-12: Flash Controller Data Register 3 ........................................................................................................................... 141
Table 8-1: SPI Header Format .................................................................................................................................................. 145
Table 8-2: Clock Polarity and Phase Combinations .................................................................................................................. 147
Table 8-3: Encrypted Data Write Order to SPIX Flash Memory ............................................................................................... 150
Table 8-4. SPIXF Master Controller Register Offsets, Names, Access and Description ........................................................... 151
Table 8-5. SPIXF Controller Configuration Register ................................................................................................................. 151
Table 8-6. SPIXF Controller Slave Select Polarity Register ....................................................................................................... 152
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