MAX32665-MAX32668 User Guide
Maxim Integrated Page 18 of 457
Table 8-7. SPIXF Controller General Control Register .............................................................................................................. 153
Table 8-8. SPIXF Controller FIFO Control and Status Register ................................................................................................. 154
Table 8-9. SPIXF Controller Special Control Register ............................................................................................................... 155
Table 8-10. SPIXF Controller Interrupt Status Register ............................................................................................................ 156
Table 8-11. SPIXF Controller Interrupt Enable Register ........................................................................................................... 157
Table 8-12. SPIXF Master Controller FIFO Register Offsets, Names, Access and Description ................................................. 158
Table 8-13. SPIXF Master Controller TX FIFO Register ............................................................................................................. 158
Table 8-14. SPIXF Master Controller TX FIFO Register ............................................................................................................. 158
Table 8-15. SPIXFM Master Register Offsets, Names, Access and Description ....................................................................... 162
Table 8-16. SPIXFM Configuration Register ............................................................................................................................. 162
Table 8-17. SPIXFM Fetch Control Register ............................................................................................................................. 163
Table 8-18. SPIXFM Mode Control Register ............................................................................................................................. 164
Table 8-19. SPIXFM Mode Data Register ................................................................................................................................. 165
Table 8-20. SPIXFM SCK Feedback Control Register ................................................................................................................ 165
Table 8-21. SPIXFM I/O Control Register ................................................................................................................................. 165
Table 8-22. SPIXFM Memory Security Control Register ........................................................................................................... 166
Table 8-23. SPIXFM Bus Idle Detection .................................................................................................................................... 166
Table 8-24. SPIXR Master Controller Register Offsets, Names, Access and Descriptions ........................................................ 168
Table 8-25. SPIXR FIFO Data Register ...................................................................................................................................... 169
Table 8-26. SPIXR Master Signals Control Register .................................................................................................................. 169
Table 8-27. SPIXR Transmit Packet Size Register ..................................................................................................................... 170
Table 8-28. SPIXR Static Configuration Register ...................................................................................................................... 170
Table 8-29. SPIXR Slave Select Timing Register ....................................................................................................................... 171
Table 8-30. SPIXR Master Baud Rate Generator ...................................................................................................................... 172
Table 8-31. SPIXR DMA Control Register ................................................................................................................................. 173
Table 8-32. SPIXR Interrupt Status Flag Register ..................................................................................................................... 174
Table 8-33. SPIXR Interrupt Enable Register ............................................................................................................................ 175
Table 8-34. SPIXR Wakeup Flag Register ................................................................................................................................. 176
Table 8-35. SPIXR Wakeup Enable Register ............................................................................................................................. 177
Table 8-36. SPIXR Active Status Register ................................................................................................................................. 177
Table 8-37. SPIXR External Memory Control Register ............................................................................................................. 177
Table 8-38: External Memory Cache Controller Register Addresses and Descriptions ........................................................... 179
Table 8-39: SRCC Cache ID Register ......................................................................................................................................... 179
Table 8-40: SRCC Memory Size Register .................................................................................................................................. 179
Table 8-41: SRCC Cache Control Register ................................................................................................................................ 179
Table 8-42: SRCC Invalidate Register ....................................................................................................................................... 180
Table 8-43: MAX32665—MAX32668 SDHC Alternate Function Mapping to SDHC Specification Pin Names ......................... 182
Table 8-44: Registers Used to Generate SD Commands .......................................................................................................... 184
Table 8-45: SDHC Register Offsets, Names and Descriptions .................................................................................................. 185
Table 8-46: SDHC SDMA System Address / Argument Register............................................................................................... 186
Table 8-47: SDHC SDMA Block Size Register ............................................................................................................................ 187
Table 8-48: SDHC SDMA Block Count Register ........................................................................................................................ 188
Table 8-49: SDHC SDMA Argument 1 Register ........................................................................................................................ 188
Table 8-50: SDHC SDMA Transfer Mode Register .................................................................................................................... 188
Table 8-51: Summary of how register settings determine type of data transfer .................................................................... 190
Table 8-52: SDHC Command Register ...................................................................................................................................... 190
Table 8-53: Relationship between Parameters and the Name of Response Type .................................................................. 191
Table 8-54: SDHC Response 0 Register .................................................................................................................................... 191
Table 8-55: SDHC Response 1 Register .................................................................................................................................... 191
Table 8-56: SDHC Response 2 Register .................................................................................................................................... 191
Table 8-57: SDHC Response 3 Register .................................................................................................................................... 192
Table 8-58: SDHC Response 4 Register .................................................................................................................................... 192
Table 8-59: SDHC Response 5 Register .................................................................................................................................... 192
To Next Page
Loading...