MAX32665-MAX32668 User Guide
Maxim Integrated Page 19 of 457
Table 8-60: SDHC Response 6 Register .................................................................................................................................... 192
Table 8-61: SDHC Response 7 Register .................................................................................................................................... 193
Table 8-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention ................................... 193
Table 8-63: Kind of SD Card Response Mapping to SDHC Response Registers ........................................................................ 193
Table 8-64: SDHC Buffer Data Port Register ............................................................................................................................ 193
Table 8-65: SDHC Present State Register ................................................................................................................................. 193
Table 8-66: SDHC Host Control 1 Register ............................................................................................................................... 196
Table 8-67: SDHC Power Control Register ............................................................................................................................... 197
Table 8-68: SDHC Block Gap Control Register ......................................................................................................................... 197
Table 8-69: SDHC Wakeup Control Register ............................................................................................................................ 199
Table 8-70: SDHC Clock Control Register ................................................................................................................................. 199
Table 8-71: SDHC Timeout Control Register ............................................................................................................................ 201
Table 8-72: SDHC Software Reset Register .............................................................................................................................. 202
Table 8-73: SDHC Normal Interrupt Status Register ................................................................................................................ 203
Table 8-74: Transfer Complete and Data Timeout Error Priority and Status ........................................................................... 205
Table 8-75: Command Complete and Command Timeout Error Priority and Status .............................................................. 205
Table 8-76: SDHC Error Interrupt Status Register .................................................................................................................... 205
Table 8-77: SDHC Normal Interrupt Status Register ................................................................................................................ 207
Table 8-78: SDHC Error Interrupt Status Enable Register ........................................................................................................ 208
Table 8-79: SDHC Normal Interrupt Signal Enable Register ..................................................................................................... 209
Table 8-80: SDHC Error Interrupt Signal Enable Register ........................................................................................................ 210
Table 8-81: SDHC Auto CMD Error Status Register .................................................................................................................. 211
Table 8-82: SDHC Host Control 2 Register ............................................................................................................................... 212
Table 8-83: SDHC Capabilities Register 0 ................................................................................................................................. 213
Table 8-84: SDHC Capabilities Register 1 ................................................................................................................................. 215
Table 8-85: SDHC Maximum Current Capabilities Register ..................................................................................................... 216
Table 8-86: SDHC Force Event Register for Auto CMD Error Status Register .......................................................................... 216
Table 8-87: SDHC Force Event Register for Error Interrupt Status .......................................................................................... 216
Table 8-88: SDHC ADMA Error Status Register ........................................................................................................................ 217
Table 8-89: SDHC ADMA System Address Register 0 ............................................................................................................... 218
Table 8-90: SDHC ADMA System Address Register 1 ............................................................................................................... 219
Table 8-91: Preset Value Register Example ............................................................................................................................. 219
Table 8-92: Preset Value Register Selection Conditions .......................................................................................................... 219
Table 8-93: SDHC Preset Value 0 to Preset Value 7 Registers ................................................................................................. 220
Table 8-94: SDHC Slot Interrupt Status Register ...................................................................................................................... 220
Table 8-95: SDHC Host Controller Version Register ................................................................................................................. 221
Table 9-1: MAX32665—MAX32668 DMAC and Channel Instances ......................................................................................... 223
Table 9-2: MAX32665—MAX32668 DMAC Source and Destination by Peripheral ................................................................. 224
Table 9-3: Data Movement from Source to DMA FIFO ............................................................................................................ 226
Table 9-4: Data Movement from the DMA FIFO to Destination .............................................................................................. 226
Table 9-5: DMA Channel Timeout Configuration ..................................................................................................................... 230
Table 9-6: DMAC Register Summary ........................................................................................................................................ 231
Table 9-7: DMACn Control Register ......................................................................................................................................... 231
Table 9-8: DMACn Interrupt Register ...................................................................................................................................... 232
Table 9-9: Standard DMA Channel 0 to Channel 7 Register Summary .................................................................................... 232
Table 9-10: DMACH Channel Registers Summary .................................................................................................................... 232
Table 9-11: DMACHn Configuration Register .......................................................................................................................... 233
Table 9-12: DMA Status Register ............................................................................................................................................. 234
Table 9-13: DMACHn Source Register ..................................................................................................................................... 235
Table 9-14: DMA Channel n Destination Register ................................................................................................................... 236
Table 9-15: DMA Channel n Count Register ............................................................................................................................ 236
Table 9-16: DMA Channel n Source Reload Register ............................................................................................................... 236
Table 9-17: DMA Channel n Destination Reload Register ....................................................................................................... 236
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