Maxim Integrated MAX32665 - Page 20

MAX32665-MAX32668 User Guide
Maxim Integrated Page 20 of 457
Table 9-18: DMA Channel n Count Reload Register ................................................................................................................ 237
Table 10-1: Common CRC Polynomials .................................................................................................................................... 239
Table 10-2: CRC Register Summary.......................................................................................................................................... 240
Table 10-3: CRC Control Register ............................................................................................................................................. 243
Table 10-4: CRC DMA Source Register ..................................................................................................................................... 243
Table 10-5: CRC DMA Destination Register ............................................................................................................................. 243
Table 10-6: CRC DMA Count Register ...................................................................................................................................... 243
Table 10-7: CRC Data Input Registers ...................................................................................................................................... 244
Table 10-8: CRC Data Output Registers ................................................................................................................................... 244
Table 10-9: CRC Polynomial Register ....................................................................................................................................... 244
Table 10-10: CRC Value Register .............................................................................................................................................. 245
Table 10-11: CRC Pseudo-Random Number Generator Register ............................................................................................. 245
Table 11-1: MAX32665—MAX32668 ADC Peripheral Pins ...................................................................................................... 246
Table 11-2: ADC Clock Frequency and ADC Conversion Time (, )............................. 249
Table 11-3: Input and Reference Scale Support by ADC Input Channel .................................................................................. 251
Table 11-4: ADC Data Register Alignment Options .................................................................................................................. 252
Table 11-5. ADC Registers Summary ........................................................................................................................................ 255
Table 11-6: ADC Control Register ............................................................................................................................................ 255
Table 11-7: ADC Status Register .............................................................................................................................................. 257
Table 11-8: ADC Data Register ................................................................................................................................................. 257
Table 11-9: ADC Interrupt Control Register ............................................................................................................................. 257
Table 11-10: ADC Limit 0 to 3 Registers ................................................................................................................................... 258
Table 12-1: UART Interrupt Conditions.................................................................................................................................... 261
Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps .................................................................... 262
Table 12-3: UART Register Summary ....................................................................................................................................... 264
Table 12-4: UART Control 0 Register ....................................................................................................................................... 264
Table 12-5: UART Control 1 Register ....................................................................................................................................... 266
Table 12-6: UART Status Register ............................................................................................................................................ 266
Table 12-7: UART Interrupt Enable Register ............................................................................................................................ 267
Table 12-8: UART Interrupt Flags Register ............................................................................................................................... 268
Table 12-9: UART Rate Integer Register .................................................................................................................................. 270
Table 12-10: UART Baud Rate Decimal Register ...................................................................................................................... 270
Table 12-11: UART FIFO Register ............................................................................................................................................. 270
Table 12-12: UART DMA Configuration Register ..................................................................................................................... 270
Table 12-13: UART Transmit FIFO Data Output Register ......................................................................................................... 271
Table 13-1: MAX32665 – MAX32668 I
2
C Peripheral Pins ........................................................................................................ 274
Table 13-2: I
2
C Bus Terminology .............................................................................................................................................. 275
Table 13-3: Calculated I
2
C Bus Clock Frequencies ................................................................................................................... 279
Table 13-4: I
2
C Slave Address Format ...................................................................................................................................... 279
Table 13-5: I
2
C Registers .......................................................................................................................................................... 292
Table 13-6: I
2
C Control 0 Register ............................................................................................................................................ 293
Table 13-7: I
2
C Status Register ................................................................................................................................................. 294
Table 13-8: I
2
C Interrupt Flag 0 Register .................................................................................................................................. 295
Table 13-9: I
2
C Interrupt Enable 0 Register ............................................................................................................................. 297
Table 13-10: I
2
C Interrupt Flag 1 Register ................................................................................................................................ 299
Table 13-11: I
2
C Interrupt Enable 1 Register ........................................................................................................................... 299
Table 13-12: I
2
C FIFO Length Register ...................................................................................................................................... 299
Table 13-13: I
2
C Receive Control 0 Register............................................................................................................................. 299
Table 13-14: I
2
C Receive Control 1 Register............................................................................................................................. 300
Table 13-15: I
2
C Transmit Control 0 Register ........................................................................................................................... 301
Table 13-16: I
2
C Transmit Control 1 Register ........................................................................................................................... 302
Table 13-17: I
2
C Data Register ................................................................................................................................................. 302
Table 13-18: I
2
C Master Mode Control Register ...................................................................................................................... 303