MAX32665-MAX32668 User Guide
Maxim Integrated Page 21 of 457
Table 13-19: I
2
C SCL Low Control Register ............................................................................................................................... 303
Table 13-20: I
2
C SCL High Control Register .............................................................................................................................. 303
Table 13-21: I
2
C Hs-Mode Clock Control Register .................................................................................................................... 304
Table 13-22: I
2
C Timeout Register ........................................................................................................................................... 304
Table 13-23: I
2
C DMA Register ................................................................................................................................................. 304
Table 13-24: I
2
C Slave Address Register ................................................................................................................................... 305
Table 14-1: MAX32665—MAX32668 SPI Instances ................................................................................................................. 307
Table 14-2: MAX32665—MAX32668 QSPI Signal Mapping ..................................................................................................... 308
Table 14-3: Four-Wire Format Signals ..................................................................................................................................... 308
Table 14-4: Three-Wire Format Signals ................................................................................................................................... 309
Table 14-5. SPI Modes Clock Phase and Polarity Operation .................................................................................................... 313
Table 14-6: QSPIn Base Address Offsets, Register Names, Access and Descriptions .............................................................. 314
Table 14-7: QSPIn FIFO Data Register ...................................................................................................................................... 315
Table 14-8: QSPIn Control 0 Register ....................................................................................................................................... 315
Table 14-9: QSPIn Transmit Packet Size Register..................................................................................................................... 316
Table 14-10: QSPIn Control 2 Register ..................................................................................................................................... 316
Table 14-11: QSPIn Slave Select Timing Register ..................................................................................................................... 318
Table 14-12: QSPIn Master Clock Configuration Registers ...................................................................................................... 319
Table 14-13: QSPIn DMA Control Registers ............................................................................................................................. 319
Table 14-14: QSPIn Interrupt Status Flags Registers................................................................................................................ 320
Table 14-15: QSPIn Interrupt Enable Registers ........................................................................................................................ 321
Table 14-16: QSPIn Wakeup Status Flags Registers ................................................................................................................. 322
Table 14-17: QSPIn Wakeup Enable Registers ......................................................................................................................... 323
Table 14-18: QSPIn Slave Select Timing Registers ................................................................................................................... 323
Table 15-1. HTimer Registers Summary ................................................................................................................................... 326
Table 15-2: HTimer Long-Interval Counter Register ................................................................................................................ 326
Table 15-3: HTimer Short-Interval Counter Register ............................................................................................................... 326
Table 15-4: HTimer Long-Interval Alarm Register .................................................................................................................... 326
Table 15-5: HTimer Short-Interval Alarm Register ................................................................................................................... 326
Table 15-6: HTimer Control Register ....................................................................................................................................... 327
Table 16-1: Timer Register Offset, Names, Access and Descriptions ...................................................................................... 345
Table 16-2: Timer Count Registers ........................................................................................................................................... 345
Table 16-3: Timer Compare Registers ...................................................................................................................................... 345
Table 16-4: Timer Interrupt Registers ...................................................................................................................................... 346
Table 16-5: Timer Control Registers ........................................................................................................................................ 346
Table 16-6: Timer Non-Overlapping Compare Registers ......................................................................................................... 348
Table 17-1: Pulse Train Engine Register Summary .................................................................................................................. 352
Table 17-2: Pulse Train Engine Global Enable/Disable Register .............................................................................................. 354
Table 17-3: Pulse Train Engine Resync Register ....................................................................................................................... 356
Table 17-4:Pulse Train Engine Stopped Interrupt Flag Register .............................................................................................. 359
Table 17-5: Pulse Train Engine Interrupt Enable Register ....................................................................................................... 361
Table 17-6: Pulse Train Engine Safe Enable Register ............................................................................................................... 363
Table 17-7: Pulse Train Engine Safe Disable Register .............................................................................................................. 364
Table 17-8: Pulse Train Engine Configuration Register ............................................................................................................ 366
Table 17-9: Pulse Train Mode Bit Pattern Register .................................................................................................................. 366
Table 17-10: Pulse Train n Loop Configuration Register .......................................................................................................... 367
Table 17-11: Pulse Train n Automatic Restart Configuration Register .................................................................................... 367
Table 18-1. MAX32665―MAX32668 RTC Counter and Alarm Registers ................................................................................. 370
Table 18-2. RTC Register Access .............................................................................................................................................. 370
Table 18-3. MAX32665―MAX32668 RTC Square Wave Output Configuration ...................................................................... 374
Table 18-4. RTC Register Summary .......................................................................................................................................... 376
Table 18-5. RTC Seconds Counter Register .............................................................................................................................. 376
Table 18-6. RTC Sub-Second Counter Register (12-bit) ........................................................................................................... 376
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