MAX32665-MAX32668 User Guide
Maxim Integrated Page 22 of 457
Table 18-7. RTC Time-of-Day Alarm Register ........................................................................................................................... 377
Table 18-8. RTC Sub-Second Alarm Register ............................................................................................................................ 377
Table 18-9. RTC Control Register ............................................................................................................................................. 377
Table 18-10. RTC 32KHz Oscillator Digital Trim Register ......................................................................................................... 379
Table 18-11. RTC 32KHz Oscillator Control Register ................................................................................................................ 379
Table 19-1: Watchdog Timer Interrupt Period fSYS_CLK = 96MHz and fPCLK = 48MHz ......................................................... 382
Table 19-2: Watchdog Timer Register Offsets, Names and Descriptions ................................................................................ 383
Table 19-3: Watchdog Timer Control Register ........................................................................................................................ 384
Table 19-4: Watchdog Timer Reset Register ........................................................................................................................... 386
Table 20-1: OWM Pin to Alternate Function Mapping ............................................................................................................ 388
Table 20-2: 1-Wire ROM Commands ....................................................................................................................................... 392
Table 20-3: 1-Wire Slave Device ROM ID Field ........................................................................................................................ 393
Table 20-4: OWM Register Summary ...................................................................................................................................... 397
Table 20-5: OWM Configuration Register ................................................................................................................................ 398
Table 20-6: OWM Clock Divisor Register ................................................................................................................................. 399
Table 20-7: OWM Control/Status Register .............................................................................................................................. 399
Table 20-8: OWM Data Register .............................................................................................................................................. 400
Table 20-9: OWM Interrupt Flag Register ................................................................................................................................ 400
Table 20-10: OWM Interrupt Enable Register ......................................................................................................................... 401
Table 21-1: USB Bus States Indicated by the Differential Pair (D+, D-) .................................................................................... 403
Table 21-2: USB Bulk IN Endpoints Options ............................................................................................................................. 405
Table 21-3: USB Isochronous IN Endpoint Options ................................................................................................................. 407
Table 21-4: USB Isochronous OUT Endpoint Options .............................................................................................................. 408
Table 21-5: USBHS Device Register Offsets, Names, Access, and Descriptions ....................................................................... 409
Table 21-6: USBHS Device Address Register ............................................................................................................................ 410
Table 21-7: USBHS Power Management Register.................................................................................................................... 410
Table 21-8: USBHS IN Endpoint Interrupt Flags Register ......................................................................................................... 411
Table 21-9: USBHS OUT Endpoint Interrupt Flags Register ..................................................................................................... 412
Table 21-10: USBHS IN Endpoint Interrupt Enable Register .................................................................................................... 412
Table 21-11: USBHS OUT Endpoint Interrupt Enable Register ................................................................................................ 414
Table 21-12: USBHS Signaling Interrupt Status Flag Register .................................................................................................. 415
Table 21-13: USBHS Signaling Interrupt Enable Register ......................................................................................................... 415
Table 21-14: USBHS Frame Number Register .......................................................................................................................... 415
Table 21-15: USBHS Register Index Select Register ................................................................................................................. 416
Table 21-16: USBHS Test Mode Register ................................................................................................................................. 416
Table 21-17: USB Memory Mapped Register Access for Endpoints 1 to 11 ............................................................................ 416
Table 21-18: USBHS IN Endpoint Maximum Packet Size Register ........................................................................................... 417
Table 21-19: USBHS IN Endpoint Lower Control and Status Register ...................................................................................... 417
Table 21-20: USBHS Endpoint 0 Control Status Register ......................................................................................................... 418
Table 21-21: USBHS IN Endpoint Upper Control Register ....................................................................................................... 419
Table 21-22: USBHS OUT Endpoint Maximum Packet Size Register ........................................................................................ 420
Table 21-23: USBHS OUT Endpoint Lower Control Status Register ......................................................................................... 421
Table 21-24: USBHS OUT Endpoint Upper Control Status Register ......................................................................................... 422
Table 21-25: USBHS Endpoint OUT FIFO Byte Count Register ................................................................................................. 423
Table 21-26: USBHS Endpoint 0 IN FIFO Byte Count Register.................................................................................................. 423
Table 21-27: USBHS FIFO for Endpoint n Register ................................................................................................................... 423
Table 21-28: USBHS Endpoint Count Info Register .................................................................................................................. 424
Table 21-29: USBHS RAM Info Register ................................................................................................................................... 424
Table 21-30: USBHS Soft Reset Control Register ..................................................................................................................... 424
Table 21-31: USBHS Early DMA Register ................................................................................................................................. 424
Table 21-32: USBHS Hi-Speed Chirp Timeout Register ............................................................................................................ 425
Table 21-33: USBHS Hi-Speed RESUME Delay Register ........................................................................................................... 425
Table 23-1. Cryptographic Accelerator DMA Sources.............................................................................................................. 431
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