Maxim Integrated MAX32665

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  MAX32665-MAX32668 User Guide 
Maxim Integrated  Page 5 of 457 
2.1  Clock Configuration ------------------------------------------------------------------------------------------------------------------- 135 
2.2  Lock Protection ------------------------------------------------------------------------------------------------------------------------- 135 
2.3  Flash Write Width --------------------------------------------------------------------------------------------------------------------- 135 
2.4  Flash Write ------------------------------------------------------------------------------------------------------------------------------ 136 
2.5  Page Erase ------------------------------------------------------------------------------------------------------------------------------- 136 
2.6  Mass Erase ------------------------------------------------------------------------------------------------------------------------------ 137 
3  Flash Error Correction Coding ------------------------------------------------------------------------------------------ 137 
4  Flash Controller Registers ----------------------------------------------------------------------------------------------- 137 
5  Flash Controller Register Details --------------------------------------------------------------------------------------- 138 
 External Memory ----------------------------------------------------------------------------------------------------- 142 
1  Overview --------------------------------------------------------------------------------------------------------------------- 142 
2  SPI Execute-in-Place Flash (SPIXF) ------------------------------------------------------------------------------------- 142 
2.1  SPIXF Master Controller -------------------------------------------------------------------------------------------------------------- 143 
2.2  SPIXF Master ---------------------------------------------------------------------------------------------------------------------------- 158 
3  SPI Execute-in-Place RAM (SPIXR) ------------------------------------------------------------------------------------- 167 
3.1  SPIXR Master Controller Registers ------------------------------------------------------------------------------------------------ 168 
3.2  SPIXR Register Details ---------------------------------------------------------------------------------------------------------------- 169 
4  SPIXR Cache Controller (SRCC) ----------------------------------------------------------------------------------------- 178 
4.1  Features ---------------------------------------------------------------------------------------------------------------------------------- 178 
4.2  Enabling the SRCC --------------------------------------------------------------------------------------------------------------------- 178 
4.3  Disabling the SRCC -------------------------------------------------------------------------------------------------------------------- 178 
4.4  SRCC Registers -------------------------------------------------------------------------------------------------------------------------- 179 
4.5  SRCC Register Details ----------------------------------------------------------------------------------------------------------------- 179 
5  Secure Digital Host Controller ------------------------------------------------------------------------------------------ 181 
5.1  Instances --------------------------------------------------------------------------------------------------------------------------------- 182 
5.2  SDHC Peripheral Clock Selection --------------------------------------------------------------------------------------------------- 183 
5.3  Usage ------------------------------------------------------------------------------------------------------------------------------------- 183 
5.4  SD Command Generation ----------------------------------------------------------------------------------------------------------- 184 
5.5  SDHC Registers ------------------------------------------------------------------------------------------------------------------------- 185 
5.6  SDHC Register Details ---------------------------------------------------------------------------------------------------------------- 186 
 Standard DMA (DMAC) ---------------------------------------------------------------------------------------------- 222 
1  Instances --------------------------------------------------------------------------------------------------------------------- 222 
2  DMA Channel Operation (DMACH) ----------------------------------------------------------------------------------- 223 
2.1  DMA Channel Arbitration and DMA Bursts ------------------------------------------------------------------------------------- 223 
2.2  DMA Source and Destination Addressing --------------------------------------------------------------------------------------- 224 
Data Movement From Source to  DMA ------------------------------------------------------------------------------------------------------- 226 
Maxim Integrated MAX32665 - Page 5

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