MAX32665-MAX32668 User Guide
Maxim Integrated Page 6 of 457
9.2.3 Data Movement From the DMA to Destination ------------------------------------------------------------------------------- 226
9.3 Usage ------------------------------------------------------------------------------------------------------------------------- 227
9.4 Count-To-Zero (CTZ) Condition ---------------------------------------------------------------------------------------- 227
9.5 Chaining Buffers ----------------------------------------------------------------------------------------------------------- 228
9.6 DMA Interrupts ------------------------------------------------------------------------------------------------------------ 230
9.7 Channel Timeout Detect ------------------------------------------------------------------------------------------------- 230
9.8 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------- 231
9.9 DMAC Registers ------------------------------------------------------------------------------------------------------------ 231
9.10 DMAC Register Details --------------------------------------------------------------------------------------------------- 231
9.11 DMA Channel Registers -------------------------------------------------------------------------------------------------- 232
9.12 DMAC Channel Registers ------------------------------------------------------------------------------------------------ 232
9.13 DMA Channel Register Details ----------------------------------------------------------------------------------------- 233
10. Cyclic Redundancy Check Engine (CRC) ----------------------------------------------------------------------- 238
10.1 Instances --------------------------------------------------------------------------------------------------------------------- 239
10.2 Linear Feedback Shift Register (LFSR) -------------------------------------------------------------------------------- 239
10.3 Registers --------------------------------------------------------------------------------------------------------------------- 240
10.4 Register Details ------------------------------------------------------------------------------------------------------------ 241
11. Analog to Digital Converter and Comparators (ADC) ------------------------------------------------------ 246
11.1 Features ---------------------------------------------------------------------------------------------------------------------- 246
11.2 Instances --------------------------------------------------------------------------------------------------------------------- 246
11.3 Architecture ----------------------------------------------------------------------------------------------------------------- 247
11.4 Clock Configuration ------------------------------------------------------------------------------------------------------- 249
11.5 Power-Up Sequence ------------------------------------------------------------------------------------------------------ 250
11.6 Conversion ------------------------------------------------------------------------------------------------------------------ 250
11.7 Reference Scaling and Input Scaling ---------------------------------------------------------------------------------- 250
11.7.1 AIN0 – AIN7 Scale Limitations ------------------------------------------------------------------------------------------------------ 251
11.7.2 Scale Limitations for All Other Input Channels --------------------------------------------------------------------------------- 251
11.7.3 Data Conversion Output Alignment ---------------------------------------------------------------------------------------------- 251
11.7.4 Data Conversion Value Equations ------------------------------------------------------------------------------------------------- 252
11.7.5 Data Limits and Out of Range Interrupts ---------------------------------------------------------------------------------------- 253
11.7.6 Power-Down Sequence--------------------------------------------------------------------------------------------------------------- 254
11.8 Comparator Operation --------------------------------------------------------------------------------------------------- 254
11.9 Registers --------------------------------------------------------------------------------------------------------------------- 255
11.10 Register Details ------------------------------------------------------------------------------------------------------------ 255
12. UART ------------------------------------------------------------------------------------------------------------------ 260
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