Maxim Integrated MAX32665 - Page 7

MAX32665-MAX32668 User Guide
Maxim Integrated Page 7 of 457
12.1 Instances --------------------------------------------------------------------------------------------------------------------- 260
12.2 UART Frame ----------------------------------------------------------------------------------------------------------------- 260
12.3 UART Interrupts ------------------------------------------------------------------------------------------------------------ 261
12.4 UART Baud Rate Clock Source ------------------------------------------------------------------------------------------ 261
12.5 UART Baud Rate Calculation -------------------------------------------------------------------------------------------- 261
12.6 UART Configuration and Operation ----------------------------------------------------------------------------------- 263
12.7 Wakeup Time --------------------------------------------------------------------------------------------------------------- 263
12.8 Hardware Flow Control -------------------------------------------------------------------------------------------------- 263
12.9 Registers --------------------------------------------------------------------------------------------------------------------- 263
12.10 Register Details ------------------------------------------------------------------------------------------------------------ 264
13. I
2
C Master/Slave Serial Communications Peripheral (I2C) ----------------------------------------------- 272
13.1 I
2
C Master/Slave Features ----------------------------------------------------------------------------------------------- 274
13.2 Instances --------------------------------------------------------------------------------------------------------------------- 274
13.3 I
2
C Overview ---------------------------------------------------------------------------------------------------------------- 275
13.3.1 I
2
C Bus Terminology ------------------------------------------------------------------------------------------------------------------- 275
13.3.2 I
2
C Transfer Protocol Operation --------------------------------------------------------------------------------------------------- 275
13.3.3 START and STOP Conditions -------------------------------------------------------------------------------------------------------- 275
13.3.4 Master Operation --------------------------------------------------------------------------------------------------------------------- 275
13.3.5 Acknowledge and Not Acknowledge --------------------------------------------------------------------------------------------- 275
13.3.6 Bit Transfer Process ------------------------------------------------------------------------------------------------------------------- 276
13.4 I
2
C Configuration and Usage -------------------------------------------------------------------------------------------- 277
13.4.1 SCL and SDA Bus Drivers ------------------------------------------------------------------------------------------------------------- 277
13.4.2 SCL Clock Configurations ------------------------------------------------------------------------------------------------------------ 277
13.4.3 SCL Clock Generation for Standard, Fast and Fast-Plus Modes ----------------------------------------------------------- 277
13.4.4 SCL Clock Generation for Hs-mode ------------------------------------------------------------------------------------------------ 278
13.4.5 I
2
C Addressing -------------------------------------------------------------------------------------------------------------------------- 279
13.4.6 I
2
C Master Mode Operation -------------------------------------------------------------------------------------------------------- 280
13.4.7 I
2
C Slave Mode Operation ----------------------------------------------------------------------------------------------------------- 283
13.4.8 I
2
C Interrupt Sources ------------------------------------------------------------------------------------------------------------------ 288
13.4.9 TX FIFO and RX FIFO ------------------------------------------------------------------------------------------------------------------ 288
13.4.10 TX FIFO Preloading ---------------------------------------------------------------------------------------------------------------- 289
13.4.11 Interactive Receive Mode (IRXM) --------------------------------------------------------------------------------------------- 290
13.4.12 Clock Stretching -------------------------------------------------------------------------------------------------------------------- 291
13.4.13 I
2
C Bus Timeout -------------------------------------------------------------------------------------------------------------------- 291
13.4.14 I
2
C DMA Control -------------------------------------------------------------------------------------------------------------------- 292
13.5 Registers --------------------------------------------------------------------------------------------------------------------- 292