EasyManua.ls Logo

NXP Semiconductors K22F series - Page 10

NXP Semiconductors K22F series
1407 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Section number Title Page
11.5.1
Pin Control Register n (PORTx_PCRn).......................................................................................................248
11.5.2
Global Pin Control Low Register (PORTx_GPCLR)..................................................................................251
11.5.3
Global Pin Control High Register (PORTx_GPCHR).................................................................................251
11.5.4
Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 252
11.5.5
Digital Filter Enable Register (PORTx_DFER)...........................................................................................252
11.5.6
Digital Filter Clock Register (PORTx_DFCR)............................................................................................253
11.5.7
Digital Filter Width Register (PORTx_DFWR).......................................................................................... 253
11.6 Functional description...................................................................................................................................................254
11.6.1 Pin control....................................................................................................................................................254
11.6.2 Global pin control........................................................................................................................................ 255
11.6.3 External interrupts........................................................................................................................................255
11.6.4 Digital filter..................................................................................................................................................256
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................259
12.1.1 Features........................................................................................................................................................ 259
12.2 Memory map and register definition.............................................................................................................................260
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 261
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................263
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 264
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 266
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 269
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 271
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 273
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................275
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................277
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................279
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................281
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................284
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
10 NXP Semiconductors

Table of Contents

Related product manuals