Timer n
Timer 1
PIT
registers
Peripheral bus
load_value
PIT
Triggers
Peripheral
bus clock
Interrupts
Figure 40-1. Block diagram of the PIT
NOTE
See the chip-specific PIT information for the number of PIT
channels used in this MCU.
40.1.2
Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
• Ability of timers to generate interrupts
• Maskable interrupts
• Independent timeout periods for each timer
40.2
Signal description
The PIT module has no external pins.
Signal description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1030 NXP Semiconductors
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