• PDB interval trigger 0 connects to DAC0 hardware trigger input.
• PDB interval trigger 1 connects to DAC1 hardware trigger input.
3.8.1.5 DAC External Trigger Input Connections
In this MCU, the following DAC external trigger inputs are implemented.
• DAC external trigger input 0: ADC0SC1A_COCO
• DAC external trigger input 1: ADC1SC1A_COCO
NOTE
Application code can set the PDBx_DACINTCn[EXT] bit to
allow DAC external trigger input when the corresponding ADC
Conversion complete flag, ADCx_SC1n[COCO], is set.
3.8.1.6 Pulse-Out Connection
Individual PDB Pulse-Out signals are connected to each CMP block and used for sample
window.
3.8.1.7
Pulse-Out Enable Register Implementation
The following table shows the comparison of pulse-out enable register at the module and
chip level.
Table 3-53. PDB pulse-out enable register
Register Module implementation Chip implementation
POnEN 7:0 - POEN
31:8 - Reserved
0 - POEN[0] for CMP0
1 - POEN[1] for CMP1
31:2 - Reserved
3.8.2 FlexTimer Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 111
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