Conversely the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• SYSRESETREQ bit in the NVIC application interrupt and reset control register
• A system reset in the DAP control register which allows the debugger to hold the
Core in reset.
9.7 AHB-AP
AHB-AP provides the debugger access to all memory and registers in the system,
including processor registers through the NVIC. System access is independent of the
processor status. AHB-AP does not do back-to-back transactions on the bus, so all
transactions are non-sequential. AHB-AP can perform unaligned and bit-band
transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP
transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported
sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets
the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch
debugging such as read/stop/reset the core. AHB-AP transactions are little endian.
For a short period at the start of a system reset event the system security status is being
determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP
Status register is accessible and can be monitored to determine when this initial period is
completed. After this initial period, if system reset is held via assertion of the RESET pin,
the debugger has access via the bus matrix to the private peripheral bus to configure the
debug IP even while system reset is asserted. While in system reset, access to other
memory and register resources, accessed over the Crossbar Switch, is blocked.
9.8
ITM
The ITM is an application-driven trace source that supports printf style debugging to
trace Operating System (OS) and application events, and emits diagnostic system
information. The ITM emits trace information as packets. There are four sources that can
generate packets. If multiple sources generate packets at the same time, the ITM
arbitrates the order in which packets are output. The four sources in decreasing order of
priority are:
1. Software trace -- Software can write directly to ITM stimulus registers. This emits
packets.
Chapter 9 Debug
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 209
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