• TPIU
• MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• FPB
• DWT
• ITM
• NVIC
• Crossbar bus switch
1
• AHB-AP
1
• Private peripheral bus
1
6.3
Boot
This section describes the boot sequence, including sources and options.
6.3.1
Boot sources
This device only supports booting from internal flash. Any secondary boot must go
through an initialization sequence in flash.
6.3.2
Boot options
The device's functional mode is controlled by the state of the EzPort chip select
(EZP_CS) pin during reset.
The device can be in single chip (default) or serial flash programming mode (EzPort).
While in single chip mode the device can be in run or various low power modes
mentioned in Power mode transitions.
Table 6-2. Mode select decoding
EzPort chip select (EZP_CS) Description
0 Serial flash programming mode (EzPort)
1 Single chip (default)
1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available
during System Reset.
Chapter 6 Reset and Boot
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 177
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