38.3.11 Pulse-Out n Enable register (PDBx_POEN)
Address: 4003_6000h base + 190h offset = 4003_6190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
POEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POEN field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
POEN PDB Pulse-Out Enable
Enables the pulse output. Only lower 8 bits are implemented in this MCU.
0 PDB Pulse-Out disabled
1 PDB Pulse-Out enabled
38.3.12 Pulse-Out n Delay register (PDBx_POnDLY)
Note: This register is internally buffered, and any values written to the register are
written to its internal buffer instead; in other words, the internal device bus does not write
directly to this register. The value in this register's internal buffer is loaded into this
register only after "1" is written to the SC[LDOK] bit.
Address:
4003_6000h base + 194h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLY1 DLY2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field Description
31–16
DLY1
PDB Pulse-Out Delay 1
Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is equal to
the DLY1. Reading this field returns the value of internal register that is effective for the current PDB cycle.
DLY2 PDB Pulse-Out Delay 2
Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to
the DLY2. Reading this field returns the value of internal register that is effective for the current PDB cycle.
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
882 NXP Semiconductors
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