NXP Semiconductors K22F series - Control Register (DMA_CR)

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_91D8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD14_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_91DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined 22.3.34/479
4000_91DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD14_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_91DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD14_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
4000_91E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined 22.3.22/469
4000_91E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined 22.3.23/469
4000_91E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined 22.3.24/470
4000_91E8
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD15_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_91E8
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD15_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_91E8
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD15_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_91EC
TCD Last Source Address Adjustment
(DMA_TCD15_SLAST)
32 R/W Undefined 22.3.28/474
4000_91F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined 22.3.29/475
4000_91F4
TCD Signed Destination Address Offset
(DMA_TCD15_DOFF)
16 R/W Undefined 22.3.30/475
4000_91F6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD15_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_91F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD15_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_91FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined 22.3.34/479
4000_91FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD15_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_91FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD15_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
22.3.5 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 441