38.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)
Note: This register is internally buffered, and any values written to the register are
written to its internal buffer instead; in other words, the internal device bus does not write
directly to this register. The value in this register's internal buffer is loaded into this
register only after "1" is written to the SC[LDOK] bit.
Address:
4003_6000h base + 1Ch offset + (40d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DLY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY1 field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DLY PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
38.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)
Address: 4003_6000h base + 150h offset + (8d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
EXT TOE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_DACINTCn field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
EXT
DAC External Trigger Input Enable
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
880 NXP Semiconductors
To Next Page
Loading...
Need help?
General
