Table 35-2. Comparator sample/filter maximum latencies (continued)
Mode #
CR1[
EN]
CR1[
WE]
CR1[
SE]
CR0[FILTER
_CNT]
FPR[FILT_P
ER]
Operation Maximum latency
1
5A 1 1 0 0x00 X Windowed mode T
PD
+ T
per
5B 1 1 0 X 0x00 T
PD
+ T
per
6 1 1 0 0x01 0x01 - 0xFF Windowed / Resampled
mode
T
PD
+ (FPR[FILT_PER] *
T
per
) + 2T
per
7 1 1 0 > 0x01 0x01 - 0xFF Windowed / Filtered mode T
PD
+ (CR0[FILTER_CNT] *
FPR[FILT_PER] x T
per
) +
2T
per
1. T
PD
represents the intrinsic delay of the analog component plus the polarity select logic. T
SAMPLE
is the clock period of the
external sample clock. T
per
is the period of the bus clock.
35.4 CMP interrupts
The CMP module is capable of generating an interrupt on either the rising- or falling-
edge of the comparator output, or both.
The following table gives the conditions in which the interrupt request is asserted and
deasserted.
When Then
SCR[IER] and SCR[CFR] are set The interrupt request is asserted
SCR[IEF] and SCR[CFF] are set The interrupt request is asserted
SCR[IER] and SCR[CFR] are cleared for a rising-edge
interrupt
The interrupt request is deasserted
SCR[IEF] and SCR[CFF] are cleared for a falling-edge
interrupt
The interrupt request is deasserted
35.5 DMA support
Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When
DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting
SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA
transfer request rather than a CPU interrupt instead. When the DMA has completed the
transfer, it sends a transfer completing indicator that deasserts the DMA transfer request
and clears the flag to allow a subsequent change on comparator output to occur and force
another DMA request.
The comparator can remain functional in STOP modes.
Chapter 35 Comparator (CMP)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 841
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