6.2 Reset
This section discusses basic reset mechanisms and sources. Some modules that cause
resets can be configured to cause interrupts instead. Consult the individual peripheral
chapters for more information.
6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset re-arm voltage level (V
POR
), the POR circuit causes a POR reset
condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low threshold (V
LVDL
). The POR and LVD bits in SRS0 register are
set following a POR.
6.2.2
System reset sources
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:
• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start PC from vector-table offset 4
• LR is set to 0xFFFF_FFFF
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them default to their
analog function after reset.
During and following a reset, the JTAG pins have their associated input pins configured
as:
• TDI in pull-up (PU)
• TCK in pull-down (PD)
• TMS in PU
and associated output pin configured as:
• TDO with no pull-down or pull-up
Reset
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
170 NXP Semiconductors
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