Note that the nTRST signal is initially configured as disabled, however once configured
to its JTAG functionality its associated input pin is configured as:
• nTRST in PU
6.2.2.1 External pin reset (PIN)
On this device, RESET is a dedicated pin. This pin is open drain and has an internal
pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the
RCM's SRS0[PIN] bit is set.
6.2.2.1.1 RESET pin filter
The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and
RCM_RPFW[RSTFLTSEL] control this functionality; see the RCM chapter. The filters
are asynchronously reset by Chip POR. The reset value for each filter assumes the
RESET pin is negated.
For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, VLLS2,
and VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic
either switches to bypass operation or has continued filtering operation depending on the
filtering mode selected. When entering VLLS0, the
RESET pin filter is disabled and
bypassed.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.
6.2.2.2
Low-voltage detect (LVD)
The chip includes a system for managing low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip
voltage. The LVD system is always enabled in hsrun, normal run, wait, or stop mode.
The LVD system is disabled when entering VLPx, LLS, or VLLSx modes.
The LVD can be configured to generate a reset upon detection of a low voltage condition
by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is
determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the
Chapter 6 Reset and Boot
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 171
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