I2Sx_MDR field descriptions (continued)
Field Description
NOTE:
When using fractional divide values, the MCLK duty cycle will not always be 50/50. See Audio
master clock.
DIVIDE MCLK Divide
Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ).
FRACT must be set equal or less than the value in the DIVIDE field.
NOTE:
When using fractional divide values, the MCLK duty cycle will not always be 50/50. See Audio
master clock.
49.4 Functional description
This section provides a complete functional description of the block.
49.4.1
SAI clocking
The SAI clocks include:
• The audio master clock
• The bit clock
• The bus clock
49.4.1.1
Audio master clock
The audio master clock is used to generate the bit clock when the receiver or transmitter
is configured for an internally generated bit clock. The transmitter and receiver can
independently select between the bus clock and up to three audio master clocks to
generate the bit clock.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock. The input clock selection and pin direction cannot be altered if
an SAI module using that audio master clock has been enabled. The MCLK divide ratio
can be altered while an SAI is using that master clock, although the change in the divide
ratio takes several cycles. MCR[DUF] can be polled to determine when the divide ratio
change has completed.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1364 NXP Semiconductors
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