42.2.7 RTC Lock Register (RTC_LR)
Address: 4003_D000h base + 18h offset = 4003_D018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 1
LRL SRL CRL TCL
1
W
Reset
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_LR field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
6
LRL
Lock Register Lock
After being cleared, this bit can be set only by VBAT POR or software reset.
0 Lock Register is locked and writes are ignored.
1 Lock Register is not locked and writes complete as normal.
5
SRL
Status Register Lock
After being cleared, this bit can be set only by VBAT POR or software reset.
0 Status Register is locked and writes are ignored.
1 Status Register is not locked and writes complete as normal.
4
CRL
Control Register Lock
After being cleared, this bit can only be set by VBAT POR.
0 Control Register is locked and writes are ignored.
1 Control Register is not locked and writes complete as normal.
3
TCL
Time Compensation Lock
After being cleared, this bit can be set only by VBAT POR or software reset.
0 Time Compensation Register is locked and writes are ignored.
1 Time Compensation Register is not locked and writes complete as normal.
Reserved This field is reserved.
This read-only field is reserved and always has the value 1.
Chapter 42 Real Time Clock (RTC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1059