• Wake-up inputs that are activated after MCU enters a low-leakage power mode
• Optional digital filters provided to qualify an external pin detect. Note that when the
LPO clock is disabled, the filters are disabled and bypassed.
17.1.2 Modes of operation
The LLWU module becomes functional on entry into a low-leakage power mode. After
recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the
LLWU continues to detect wake-up events until the user has acknowledged the wake-up
via a write to PMC_REGSC[ACKISO].
17.1.2.1 LLS mode
Wake-up events due to external pin inputs (LLWU_Px) and internal module interrupt
inputs (LLWU_MxIF) result in an interrupt flow when exiting LLS.
NOTE
The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit Stop mode on an LLS recovery.
17.1.2.2
VLLS modes
All wakeup and reset events result in VLLS exit via a reset flow.
17.1.2.3
Non-low leakage modes
The LLWU is not active in all non-low leakage modes where detection and control logic
are in a static state. The LLWU registers are accessible in non-low leakage modes and are
available for configuring and reading status when bus transactions are possible.
When the wake-up pin filters are enabled, filter operation begins immediately. If a low
leakage mode is entered within five LPO clock cycles of an active edge, the edge event
will be detected by the LLWU.
Introduction
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
380 NXP Semiconductors
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