NXP Semiconductors K22F series - Status Register (Spix_Sr)

45.3.5 Status Register (SPIx_SR)
SR contains status and flag bits. The bits reflect the status of the module and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear flag
bits in the SR by writing a 1 to them. Writing a 0 to a flag bit has no effect. This register
may not be writable in Module Disable mode due to the use of power saving
mechanisms.
Address:
Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TCF
TXRXS
0
EOQF
TFUF
0
TFFF
0 0 0 0 0
RFOF
0
RFDF
0
W
w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXCTR TXNXTPTR RXCTR POPNXTPTR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_SR field descriptions
Field Description
31
TCF
Transfer Complete Flag
Indicates that all bits in a frame have been shifted out. TCF remains set until it is cleared by writing a 1 to
it.
0 Transfer not complete.
1 Transfer complete.
30
TXRXS
TX and RX Status
Reflects the run status of the module.
Table continues on the next page...
Memory Map/Register Definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1142 NXP Semiconductors