45.4.2.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX
FIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Every
time an SPI frame is transferred to the RX FIFO, the RX FIFO Counter is incremented by
one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the
SR is set indicating an overflow condition. Depending on the state of the ROOE bit in the
MCR, the data from the transfer that generated the overflow is either ignored or shifted in
to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift
register. If the ROOE bit is cleared, the incoming data is ignored.
45.4.2.5.2 Draining the RX FIFO
Host CPU or a DMA can remove (pop) entries from the RX FIFO by reading the module
POP RX FIFO Register (POPR). A read of the POPR decrements the RX FIFO Counter
by one. Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO
Counter remains unchanged. The data, read from the empty RX FIFO, is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the SR is set. The
RFDF bit is cleared when the RX_FIFO is empty and the DMA controller indicates that a
read from POPR is complete or by writing a 1 to it.
45.4.3
Module baud rate and clock delay generation
The SCK frequency and the delay values for serial transfer are generated by dividing the
system clock frequency by a prescaler and a scaler with the option for doubling the baud
rate. The following figure shows conceptually how the SCK signal is generated.
System Clock
Prescaler
1
Scaler
1+DBR
SCK
Figure 45-4. Communications clock prescalers and scalers
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1156 NXP Semiconductors
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