45.2.6 SIN—Serial Input
Master mode: Serial Input (I)—Receives serial data.
Slave mode: Serial Input (I)—Receives serial data.
45.2.7 SOUT—Serial Output
Master mode: Serial Output (O)—Transmits serial data.
Slave mode: Serial Output (O)—Transmits serial data.
45.3
Memory Map/Register Definition
Register accesses to memory addresses that are reserved or undefined result in a transfer
error. Any Write access to the POPR and RXFRn also results in a transfer error.
SPI memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_C000 Module Configuration Register (SPI0_MCR) 32 R/W 0000_4001h 45.3.1/1132
4002_C008 Transfer Count Register (SPI0_TCR) 32 R/W 0000_0000h 45.3.2/1135
4002_C00C
Clock and Transfer Attributes Register (In Master Mode)
(SPI0_CTAR0)
32 R/W 7800_0000h 45.3.3/1136
4002_C00C
Clock and Transfer Attributes Register (In Slave Mode)
(SPI0_CTAR0_SLAVE)
32 R/W 7800_0000h 45.3.4/1140
4002_C010
Clock and Transfer Attributes Register (In Master Mode)
(SPI0_CTAR1)
32 R/W 7800_0000h 45.3.3/1136
4002_C02C Status Register (SPI0_SR) 32 R/W 0200_0000h 45.3.5/1142
4002_C030
DMA/Interrupt Request Select and Enable Register
(SPI0_RSER)
32 R/W 0000_0000h 45.3.6/1145
4002_C034 PUSH TX FIFO Register In Master Mode (SPI0_PUSHR) 32 R/W 0000_0000h 45.3.7/1147
4002_C034
PUSH TX FIFO Register In Slave Mode
(SPI0_PUSHR_SLAVE)
32 R/W 0000_0000h 45.3.8/1149
4002_C038 POP RX FIFO Register (SPI0_POPR) 32 R 0000_0000h 45.3.9/1149
4002_C03C Transmit FIFO Registers (SPI0_TXFR0) 32 R 0000_0000h
45.3.10/
1150
4002_C040 Transmit FIFO Registers (SPI0_TXFR1) 32 R 0000_0000h
45.3.10/
1150
4002_C044 Transmit FIFO Registers (SPI0_TXFR2) 32 R 0000_0000h
45.3.10/
1150
4002_C048 Transmit FIFO Registers (SPI0_TXFR3) 32 R 0000_0000h
45.3.10/
1150
Table continues on the next page...
Memory Map/Register Definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1130 NXP Semiconductors
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