28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)
Address: 4001_F000h base + 4h offset = 4001_F004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
B0RWSC[3:0]
CLCK_WAY[3:0]
0
0
B0MW[1:0] 0
W
CINV_WAY[3:0]
S_B_
INV
Reset
0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CRC[2:0]
B0DCE
B0ICE
B0DPE
B0IPE
B0SEBE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
FMC_PFB0CR field descriptions
Field Description
31–28
B0RWSC[3:0]
Bank 0 Read Wait State Control
This read-only field defines the number of wait states required to access the bank 0 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
27–24
CLCK_WAY[3:0]
Cache Lock Way x
These bits determine if the given cache way is locked such that its contents will not be displaced by future
misses.
The bit setting definitions are for each bit in the field.
0 Cache way is unlocked and may be displaced
1 Cache way is locked and its contents are not displaced
23–20
CINV_WAY[3:0]
Cache Invalidate Way x
Table continues on the next page...
Memory map and register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
602 NXP Semiconductors
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