NXP Semiconductors K22F series - Page 601

FMC_PFAPR field descriptions (continued)
Field Description
16
M0PFD
Master 0 Prefetch Disable
These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
15–10
Reserved
This field is reserved.
This read-only bitfield is reserved and is reset to zero. Do not write to this bitfield or indeterminate results
will occur.
9–8
Reserved
This field is reserved.
7–6
Reserved
This field is reserved.
5–4
M2AP[1:0]
Master 2 Access Protection
This field controls whether read and write access to the flash is allowed, based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
3–2
M1AP[1:0]
Master 1 Access Protection
This field controls whether read and write access to the flash is allowed, based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
M0AP[1:0] Master 0 Access Protection
This field controls whether read and write access to the flash is allowed, based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
Chapter 28 Flash Memory Controller (FMC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 601