24.7.6 Watchdog Window Register Low (WDOG_WINL)
NOTE
You must set the Window Register value lower than the Time-
out Value Register.
Address: 4005_2000h base + Ah offset = 4005_200Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WINLOW
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
WDOG_WINL field descriptions
Field Description
WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is
defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed
only when the timer reaches a value greater than or equal to this window length value. A refresh outside of
this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system.
24.7.7 Watchdog Refresh register (WDOG_REFRESH)
Address: 4005_2000h base + Ch offset = 4005_200Ch
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WDOGREFRESH
Write
Reset
1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0
WDOG_REFRESH field descriptions
Field Description
WDOGREFRESH Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written
to this register refreshes the WDOG and prevents it from resetting the system. Writing a value other than
the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
IRQRSTEN is set, it interrupts and then resets the system.
24.7.8 Watchdog Unlock register (WDOG_UNLOCK)
Address: 4005_2000h base + Eh offset = 4005_200Eh
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
WDOGUNLOCK
Write
Reset
1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0
Chapter 24 Watchdog Timer (WDOG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 533
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