Chapter 46
Inter-Integrated Circuit (I2C)
46.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The inter-integrated circuit (I
2
C, I2C, or IIC) module provides a method of
communication between a number of devices.
The interface is designed to operate up to 100 kbit/s with maximum bus loading and
timing. The I2C device is capable of operating at higher baud rates, up to a maximum of
clock/20, with reduced bus loading. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of
400 pF. The I2C module also complies with the System Management Bus (SMBus)
Specification, version 2.
46.1.1
Features
The I2C module has the following features:
•
Compatible with The I
2
C-Bus Specification
• Multimaster operation
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1181
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