47.3.10 UART Match Address Registers 2 (UARTx_MA2)
These registers can be read and written at anytime. The MA1 and MA2 registers are
compared to input data addresses when the most significant bit is set and the associated
C4[MAEN] field is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded.
Address: Base address + 9h offset
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_MA2 field descriptions
Field Description
MA Match Address
47.3.11 UART Control Register 4 (UARTx_C4)
Address: Base address + Ah offset
Bit 7 6 5 4 3 2 1 0
Read
MAEN1 MAEN2 M10 BRFA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C4 field descriptions
Field Description
7
MAEN1
Match Address Mode Enable 1
See Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when
C7816[ISO7816E] is set/enabled.
6
MAEN2
Match Address Mode Enable 2
See Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when
C7816[ISO7816E] is set/enabled.
Table continues on the next page...
Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1237
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