NOTE
Before executing the WFI instruction, the last register written to
must be read back. This ensures that all register writes
associated with setting up the low power mode being entered
have completed before the MCU enters the low power mode.
Failure to do this may result in the low power mode not being
entered correctly.
SMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 15.3.1/354
4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 15.3.2/355
4007_E002 Stop Control Register (SMC_STOPCTRL) 8 R/W 03h 15.3.3/357
4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 15.3.4/358
15.3.1 Power Mode Protection register (SMC_PMPROT)
This register provides protection for entry into any low-power run or stop mode. The
enabling of the low-power run or stop mode occurs by configuring the Power Mode
Control register (PMCTRL).
The PMPROT register can be written only once after any system reset.
If the MCU is configured for a disallowed or reserved power mode, the MCU remains in
its current power mode. For example, if the MCU is in normal RUN mode and AVLP is
0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and
PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the Reset
section details for more information.
Address:
4007_E000h base + 0h offset = 4007_E000h
Bit 7 6 5 4 3 2 1 0
Read
AHSRUN
0
AVLP
0
ALLS
0
AVLLS
0
Write
Reset
0 0 0 0 0 0 0 0
Memory map and register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
354 NXP Semiconductors
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