MCG_C1 field descriptions (continued)
Field Description
0 External reference clock is selected.
1 The slow internal reference clock is selected.
1
IRCLKEN
Internal Reference Clock Enable
Enables the internal reference clock for use as MCGIRCLK.
0 MCGIRCLK inactive.
1 MCGIRCLK active.
0
IREFSTEN
Internal Reference Stop Enable
Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
0 Internal reference clock is disabled in Stop mode.
1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI
modes before entering Stop mode.
25.3.2 MCG Control 2 Register (MCG_C2)
Address: 4006_4000h base + 1h offset = 4006_4001h
Bit 7 6 5 4 3 2 1 0
Read
LOCRE0 FCFTRIM RANGE HGO EREFS LP IRCS
Write
Reset
1 x* 0 0 0 0 0 0
* Notes:
x = Undefined at reset.•
MCG_C2 field descriptions
Field Description
7
LOCRE0
Loss of Clock Reset Enable
Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference
clock. The LOCRE0 only has an affect when CME0 is set.
0 Interrupt request is generated on a loss of OSC0 external reference clock.
1 Generate a reset request on a loss of OSC0 external reference clock.
6
FCFTRIM
Fast Internal Reference Clock Fine Trim
FCFTRIM
1
controls the smallest adjustment of the fast internal reference clock frequency. Setting
FCFTRIM increases the period and clearing FCFTRIM decreases the period by the smallest amount
possible.
If an FCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this bit.
5–4
RANGE
Frequency Range Select
Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC)
chapter for more details and the device data sheet for the frequency ranges used.
Table continues on the next page...
Chapter 25 Multipurpose Clock Generator (MCG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 545
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