EWM_CTRL field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
INTEN
Interrupt Enable.
This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt
request, user should clear this bit by writing 0.
2
INEN
Input Enable.
This bit when set, enables the EWM_in port.
1
ASSIN
EWM_in's Assertion State Select.
Default assert state of the EWM_in signal is logic zero. Setting the ASSIN bit inverts the assert state of
EWM_in signal to a logic one.
0
EWMEN
EWM enable.
This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the
EWM_out signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until a
next reset, due to the write-once nature of this bit.
23.3.2 Service Register (EWM_SERV)
The SERV register provides the interface from the CPU to the EWM module. It is write-
only and reads of this register return zero.
Address:
4006_1000h base + 1h offset = 4006_1001h
Bit 7 6 5 4 3 2 1 0
Read 0
Write SERVICE
Reset
0 0 0 0 0 0 0 0
EWM_SERV field descriptions
Field Description
SERVICE The EWM refresh mechanism requires the CPU to write two values to the SERV register: a first data byte
of 0xB4, followed by a second data byte of 0x2C. The EWM refresh is invalid if either of the following
conditions is true.
• The first or second data byte is not written correctly.
• The second data byte is not written within a fixed number of peripheral bus cycles of the first data
byte. This fixed number of cycles is called EWM_refresh_time.
23.3.3 Compare Low Register (EWM_CMPL)
The CMPL register is reset to zero after a CPU reset. This provides no minimum time for
the CPU to refresh the EWM counter.
Chapter 23 External Watchdog Monitor (EWM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 513
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