The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in
the RCM is set indicating that the chip is recovering from a low power mode. Code
execution begins; however, the I/O pins are held in their pre low power mode entry
states, and the system oscillator and MCG registers are reset (even if EREFSTEN had
been set before entering VLLSx). Software must clear this hold by writing a 1 to the
ACKISO bit in the Regulator Status and Control Register in the PMC module.
NOTE
To avoid unwanted transitions on the pins, software must re-
initialize the I/O pins to their pre-low-power mode entry states
before releasing the hold.
If the oscillator was configured to continue running during VLLSx modes, it must be re-
configured before the ACKISO bit is cleared. The oscillator configuration within the
MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is
cleared unless the register is re-configured.
7.5
Power mode transitions
The following figure shows the power mode transitions. Any reset always brings the chip
back to the normal run state. In run, wait, and stop modes active power regulation is
enabled. The VLPx modes offer a lower power operating mode than normal modes.
VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest
power stop modes based on amount of logic or memory that is required to be retained by
the application.
Power mode transitions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
188 NXP Semiconductors
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