Chapter 51
JTAG Controller (JTAGC)
51.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format.
51.1.1
Block diagram
The following is a simplified block diagram of the JTAG Controller (JTAGC) block.
Refer to the chip-specific configuration information as well as Register description for
more information about the JTAGC registers.
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1383
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