Chapter 9
Debug
9.1 Introduction
This device's debug is based on the ARM coresight architecture and is configured in each
device to provide the maximum flexibility as allowed by the restrictions of the pinout and
other available resources.
Four debug interfaces are supported:
• IEEE 1149.1 JTAG
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface(1-pin asynchronous mode only)
The basic Cortex-M4 debug architecture is very flexible. The following diagram shows
the topology of the core debug architecture and its components.
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 199
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