VREF_TRM field descriptions (continued)
Field Description
000000 Min
.... ....
111111 Max
37.2.2 VREF Status and Control Register (VREF_SC)
This register contains the control bits used to enable the internal voltage reference and to
select the buffer mode to be used.
Address:
4007_4000h base + 1h offset = 4007_4001h
Bit 7 6 5 4 3 2 1 0
Read
VREFEN REGEN ICOMPEN
0 0 VREFST
MODE_LV
Write
Reset
0 0 0 0 0 0 0 0
VREF_SC field descriptions
Field Description
7
VREFEN
Internal Voltage Reference enable
This bit is used to enable the bandgap reference within the Voltage Reference module.
NOTE:
After the VREF is enabled, turning off the clock to the VREF module via the corresponding clock
gate register will not disable the VREF. VREF must be disabled via this VREFEN bit.
0 The module is disabled.
1 The module is enabled.
6
REGEN
Regulator enable
This bit is used to enable the internal 1.75 V regulator to produce a constant internal voltage supply in
order to reduce the sensitivity to external supply noise and variation. If it is desired to keep the regulator
enabled in very low power modes, refer to the Chip Configuration details for a description on how this can
be achieved.
This bit should be written to 1 to achieve the performance stated in the data sheet.
NOTE:
See section "Internal voltage regulator" for details on the required sequence to enable the internal
regulator.
0 Internal 1.75 V regulator is disabled.
1 Internal 1.75 V regulator is enabled.
5
ICOMPEN
Second order curvature compensation enable
This bit should be written to 1 to achieve the performance stated in the data sheet.
Table continues on the next page...
Chapter 37 Voltage Reference (VREFV1)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 861
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