SPIx_RXFRn field descriptions (continued)
Field Description
45.4 Functional description
The module supports full-duplex, synchronous serial communications between chips and
peripheral devices. The SPI configuration transfers data serially using a shift register and
a selection of programmable transfer attributes.
The module has the following configuration
• The SPI Configuration in which the module operates as a basic SPI or a queued SPI.
The DCONF field in the Module Configuration Register (MCR) determines the module
Configuration. SPI configuration is selected when DCONF within SPIx_MCR is 0b00.
The CTARn registers hold clock and transfer attributes. The SPI configuration allows to
select which CTAR to use on a frame by frame basis by setting a field in the SPI
command.
See Clock and Transfer Attributes Register (In Master Mode) (SPI_CTARn) for
information on the fields of CTAR registers.
Typical master to slave connections are shown in the following figure. When a data
transfer operation is performed, data is serially shifted a predetermined number of bit
positions. Because the modules are linked, data is exchanged between the master and the
slave. The data that was in the master shift register is now in the shift register of the
slave, and vice versa. At the end of a transfer, the Transfer Control Flag(TCF) bit in the
Shift Register(SR) is set to indicate a completed frame transfer.
Shift Register
Baud Rate
Generator
Shift Register
SOUT
SCK
PCSx
SPI SlaveSPI Master
SIN
SOUT
SIN
SS
SCK
Figure 45-3. Serial protocol overview
Chapter 45 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1151
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