NOTE
In Stop mode, the I2C module supports slave receive mode
only. To avoid I2C bus conflicts during wakeup from Stop
mode, software must ensure the following before entering Stop
mode:
• I2C data transfers have completed.
• The I2C module is in slave receive mode (C1[MST]=0,
C1[TX]=0).
NOTE
During the wake-up process, if an external master continues to
send data to the slave, the baud rate under Stop mode must be
less than 50 kbit/s. To avoid the slower baud rate under Stop
mode, the master can add a short delay in firmware to wait until
the wake-up process is complete and then send data.
NOTE
Wake-up caused by an address match is not supported for
SMBus mode.
NOTE
After I2C address matching wake-up, the master must wait a
time long enough for the slave ISR to finish running and resend
start or repeat start signals.
For the SRW bit to function properly, it only supports Address
+Write to wake up by I2C address matching. Before entering
the next low power mode, Address+Write must be sent to
change the SRW status.
46.4.9
DMA support
If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an
interrupt request.
If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMA
request instead. DMA requests are generated by the transfer complete flag (TCF).
If the DMAEN bit is set, only the TCF initiates a DMA request. All other events generate
CPU interrupts.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1210 NXP Semiconductors
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