NOTE
An event is emitted each time a counter overflows.
• The DWT can be configured to emit PC samples at defined intervals, and to emit
interrupt event information.
9.12 Debug in Low Power Modes
In low power modes in which the debug modules are kept static or powered off, the
debugger cannot gather any debug data for the duration of the low power mode. In the
case that the debugger is held static, the debug port returns to full functionality as soon as
the low power mode exits and the system returns to a state with active debug. In the case
that the debugger logic is powered off, the debugger is reset on recovery and must be
reconfigured once the low power mode is exited.
Power mode entry logic monitors Debug Power Up and System Power Up signals from
the debug port as indications that a debugger is active. These signals can be changed in
RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to
enter stop or VLPS, FCLK continues to run to support core register access. In these
modes in which FCLK is left active the debug modules have access to core registers but
not to system memory resources accessed via the crossbar.
With debug enabled, transitions from Run directly to VLPS are not allowed and result in
the system entering Stop mode instead. Status bits within the MDM-AP Status register
can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled,
transitions from Run--> VLPR --> VLPS are still possible but also result in the system
entering Stop mode instead.
In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the
debug modules retain their state but no debug activity is possible.
NOTE
When using cJTAG and entering LLS mode, the cJTAG
controller must be reset on exit from LLS mode.
Going into a VLLSx mode causes all the debug controls and settings to be reset. To give
time to the debugger to sync up with the HW, the MDM-AP Control register can be
configured hold the system in reset on recovery so that the debugger can regain control
and reconfigure debug logic prior to the system exiting reset and resuming operation.
Chapter 9 Debug
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 211
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