Generally, more than one slave device can be connected to the module master. 6
Peripheral Chip Select (PCS) signals of the module masters can be used to select which
of the slaves to communicate with. Refer to the chip specific section for details on the
number of PCS signals used in this chip.
The SPI configuration shares transfer protocol and timing properties which are described
independently of the configuration in Transfer formats. The transfer rate and delay
settings are described in Module baud rate and clock delay generation.
45.4.1 Start and Stop of module transfers
The module has two operating states: Stopped and Running. Both the states are
independent of it's configuration. The default state of the module is Stopped. In the
Stopped state, no serial transfers are initiated in Master mode and no transfers are
responded to in Slave mode. The Stopped state is also a safe state for writing the various
configuration registers of the module without causing undetermined results. In the
Running state serial transfers take place.
The TXRXS bit in the SR indicates the state of module. The bit is set if the module is in
Running state.
The module starts or transitions to Running when all of the following conditions are true:
• SR[EOQF] bit is clear
• Chip is not in the Debug mode or the MCR[FRZ] bit is clear
• MCR[HALT] bit is clear
The module stops or transitions from Running to Stopped after the current frame when
any one of the following conditions exist:
• SR[EOQF] bit is set
• Chip in the Debug mode and the MCR[FRZ] bit is set
• MCR[HALT] bit is set
State transitions from Running to Stopped occur on the next frame boundary if a transfer
is in progress, or immediately if no transfers are in progress.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1152 NXP Semiconductors
To Next Page
Loading...
Need help?
General
