Chapter 16
Power Management Controller (PMC)
16.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The power management controller (PMC) contains the internal voltage regulator, power
on reset (POR), and low voltage detect system (LVD).
See AN4503: Power Management for Kinetis MCUs for further details on using the
PMC.
16.2
Features
A list of included PMC features can be found here.
• Internal voltage regulator
• Active POR providing brown-out detect
• Low-voltage detect supporting two low-voltage trip points with four warning levels
per trip point
16.3
Low-voltage detect (LVD) system
This device includes a system to guard against low-voltage conditions. This protects
memory contents and controls MCU system states during supply voltage variations.
The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a
user-selectable trip voltage: high (V
LVDH
) or low (V
LVDL
). The trip voltage is selected by
LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes.
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 371
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