USBx_OTGISTAT field descriptions (continued)
Field Description
5
LINE_STATE_
CHG
This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change
for 1 millisecond, and the value of the line state is different from the last time when the line state was
stable. It is set on transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
Changes in J-state while SE0 is true do not cause an interrupt. This interrupt can be used in detecting
Reset, Resume, Connect, and Data Line Pulse signaling.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
Software should not change the value of this bitfield.
2
Reserved
This field is reserved.
Software should not change the value of this bitfield.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
Software should not change the value of this bitfield.
43.4.6 OTG Interrupt Control register (USBx_OTGICR)
Enables the corresponding interrupt status bits defined in the OTG Interrupt Status
Register.
Address:
4007_2000h base + 14h offset = 4007_2014h
Bit 7 6 5 4 3 2 1 0
Read
Reserved
ONEMSEC
EN
LINESTATE
EN
0
Reserved Reserved
0
Reserved
Write
Reset
0 0 0 0 0 0 0 0
USBx_OTGICR field descriptions
Field Description
7
Reserved
Software must not change the value of this bitfield.
This field is reserved.
0 The ID interrupt is disabled
1 The ID interrupt is enabled
6
ONEMSECEN
One Millisecond Interrupt Enable
0 Diables the 1ms timer interrupt.
1 Enables the 1ms timer interrupt.
5
LINESTATEEN
Line State Change Interrupt Enable
0 Disables the LINE_STAT_CHG interrupt.
1 Enables the LINE_STAT_CHG interrupt.
Table continues on the next page...
Chapter 43 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1087
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