1. Caution: If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock
selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG
clock mode switch to a non low power clock mode must be avoided.
NOTE
For the chip-specific modes of operation, see the power
management chapter of this MCU.
25.4.1.2 MCG mode switching
C1[IREFS] can be changed at any time, but the actual switch to the newly selected
reference clocks is shown by S[IREFST]. When switching between engaged internal and
engaged external modes, the FLL will begin locking again after the switch is completed.
C1[CLKS] can also be changed at any time, but the actual switch to the newly selected
clock is shown by S[CLKST]. If the newly selected clock is not available, the previous
clock will remain selected.
The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1.
If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL
engaged external (FEE) mode, the MCGOUTCLK switches to the new selected DCO
range within three clocks of the selected DCO clock. After switching to the new DCO
(indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for
several reference cycles. The FLL lock time is provided in the device data sheet as
t
fll_acquire
.
25.4.2
Low-power bit usage
C2[LP] is provided to allow the FLL or PLL to be disabled and thus conserve power
when these systems are not being used. C4[DRST_DRS] can not be written while C2[LP]
is 1. However, in some applications, it may be desirable to enable the FLL or PLL and
allow it to lock for maximum accuracy before switching to an engaged mode. Do this by
writing 0 to C2[LP].
25.4.3
MCG Internal Reference Clocks
This module supports two internal reference clocks with nominal frequencies of 32 kHz
(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by
programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz.
Chapter 25 Multipurpose Clock Generator (MCG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 561
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