38.4 Functional description
38.4.1 PDB pre-trigger and trigger outputs
The PDB contains a counter whose output is compared to several different digital values.
If the PDB is enabled, then a trigger input event will reset the counter and make it start to
count. A trigger input event is defined as a rising edge being detected on a selected
trigger input source, or if a software trigger is selected and SC[SWTRIG] is written with
1. For each channel, a delay m determines the time between assertion of the trigger input
event to the time at which changes in the pre-trigger m output signal are started. The time
is defined as:
•
Trigger input event to pre-trigger m = (prescaler × multiplication factor × delay m) +
2 peripheral clock cycles
• Add 1 additional peripheral clock cycle to determine the time when the channel
trigger output changes.
Each channel is associated with 1 ADC block. PDB channel n pre-trigger outputs 0 to M;
each pre-trigger output is connected to ADC hardware trigger select and hardware trigger
inputs. The pre-triggers are used to precondition the ADC block before the actual trigger
occurs. When the ADC receives the rising edge of the trigger, the ADC will start the
conversion according to the precondition determined by the pre-triggers. The ADC
contains M sets of configuration and result registers, allowing it to alternate conversions
between M different analog sources (like a ping-pong game). The pre-trigger outputs are
used to specify which signal will be sampled next. When a pre-trigger m is asserted, the
ADC conversion is triggered with set m of the configuration and result registers.
The waveforms shown in the following diagram show the pre-trigger and trigger outputs
of PDB channel n. The delays can be independently set using the CHnDLYm registers,
and the pre-triggers can be enabled or disabled in CHnC1[EN[m]].
Chapter 38 Programmable Delay Block (PDB)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 883
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