Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on
the device causes the bus cycle to be terminated with an error followed by the appropriate
response in the requesting bus master.
4.5 Peripheral bridge (AIPS-Lite) memory map
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.5.1
Read-after-write sequence and required serialization of
memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
NOTE
One factor contributing to these situations is processor write
buffering. The processor architecture has a programmable
configuration bit to disable write buffering:
ACTLR[DISDEFWBUF]. However, disabling buffered writes
is likely to degrade system performance much more than simply
performing the required memory serialization for the situations
that truly require it.
Peripheral bridge (AIPS-Lite) memory map
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
144 NXP Semiconductors
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