MCM_ISCR field descriptions (continued)
Field Description
8
FIOC
FPU invalid operation interrupt status
This read-only bit is a copy of the core’s FPSCR[IOC] bit and signals an illegal operation has been
detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit.
0 No interrupt
1 Interrupt occurred
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
18.2.5 Compute Operation Control Register (MCM_CPO)
This register controls the Compute Operation.
Address:
E008_0000h base + 40h offset = E008_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CPOWOI
CPOACK
CPOREQ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
404 NXP Semiconductors
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