The EWM_out signal remains deasserted when the EWM is being regularly refreshed by
the CPU within the programmable refresh window, indicating that the application code is
executed as expected.
The EWM_out signal is asserted in any of the following conditions:
• The EWM refresh occurs when the counter value is less than CMPL value.
• The EWM counter value reaches the CMPH value, and no EWM refresh has
occurred.
• If functionality of EWM_in pin is enabled and EWM_in pin is asserted while
refreshing the EWM.
• After any reset (by the virtue of the external pull-down mechanism on the
EWM_out
pin)
The EWM_out is asserted after any reset by the virtue of the external pull-down
mechanism on the EWM_out signal. Then, to deassert the EWM_out signal, set EWMEN
bit in the CTRL register to enable the EWM.
If the
EWM_out signal shares its pad with a digital I/O pin, on reset this actual pad defers
to being an input signal. The pad state is controlled by the EWM_out signal only after the
EWM is enabled by the EWMEN bit in the CTRL register.
Note
EWM_out pad must be in pull down state when EWM
functionality is used and when EWM is under Reset.
23.4.2
The EWM_in Signal
The EWM_in is a digital input signal for safety status of external safety circuits, that
allows an external circuit to control the assertion of the EWM_out signal. For example, in
the application, an external circuit monitors a critical safety function, and if there is fault
with safety function, the external circuit can then actively initiate the EWM_out signal
that controls the gating circuit.
The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register
is cleared, as after any reset.
On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in
functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted
state prior to the CPU start refreshing the EWM. This ensures that the
EWM_out stays in
the deasserted state; otherwise, the EWM_out output signal is asserted.
Functional Description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
516 NXP Semiconductors
To Next Page
Loading...
Need help?
General
